FIG. 1 is a schematic block diagram of an exemplary conventional serializer/deserializer (SerDes) communication “macrocell” 100 (often referred to as a “macro”). As shown in FIG. 1, the exemplary SerDes communication macrocell 100 typically comprises multiple channels (Channel 0, Channel 1, . . . , Channel P). Typically, each channel performs its own CDR function. A phase locked loop (PLL) 102 provides a reference clock, such as a bit rate clock, 104 that is used by each channel to synchronize transmissions, in a known manner. Individual SerDes channels (Channel 0 . . . Channel P) can be combined together to provide a multiple channel configuration, often referred to as a communication pipe, in a known manner. In a multiple channel configuration, parallel data should be serialized using serializers 110-0 through 110-P in such a manner that the corresponding serial streams have a limited skew (typically on the order of 1.25 unit intervals (UI)). The serial data rate and the number of channels used as one pipe may change dynamically. The individual channels must be synchronized with the other channels used within the same communication pipe. In addition, the number of channels may span across several SerDes macros 100, but still must be synchronized.
A number of techniques have been proposed or suggested for synchronizing individual channels in a multi-channel configuration of a SerDes macrocell. For example, one known technique employs a constantly running synchronization pulse (usually at the byte rate clock) to synchronize individual channels. This technique, however, consumes significant power due to the distribution of the synchronization signal through multiple channels. In addition, this technique requires a precise timing relation between the synchronization pulse and the higher rate bit clock. If this timing relation changes significantly, an error in the serial bit stream can be introduced.
Another technique for synchronizing individual channels employs a synchronous release of a reset with the bit rate clock stopped and resumed after the reset is released. This “synchronous reset” method cannot be used when a number of channels are added on-the-fly because the channels currently in use will experience interruption in their transmit functionality. When multiple SerDes macros are used within the same pipe, a synchronous reset has to be distributed between the macros with one macro designated as a master device and the remaining macros serving as slave devices. When one of the SerDes macros is designated as a master device, however, this particular macro cannot be powered down.
A need therefore exists for improved methods and apparatus for multiple channel synchronization in SerDes macrocells.